Apparatus and method for achieving high-speed data read...

G - Physics – 06 – F

Patent

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G06F 12/00 (2006.01) G06F 12/02 (2006.01)

Patent

CA 2116314

An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes a data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage means output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage means hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.

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