Apparatus and method for an extended arithmetic logic unit...

Details Apparatus and method for an extended arithmetic logic unit... Apparatus and method for an extended arithmetic logic unit...

G - Physics

06

F

354/204

G06F 7/48 (2006.01) G06F 7/50 (2006.01) G06F 7/544 (2006.01)

Patent

CA 1286779

APPARATUS AND METHOD FOR AN EXTENDED ARITHMETIC LOGIC UNIT FOR EXPEDITING SELECTED FLOATING POINT OPERATIONS ABSTRACT Apparatus and method are described for expediting the alignment of the fraction portion of operands in the floating point operations. The alignment is performed in the arithmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arithmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.

566752

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