Apparatus and method for coding/decoding block low density...

H - Electricity – 04 – L

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H04L 1/00 (2006.01)

Patent

CA 2531806

A method for generating a parity check matrix of a block LDPC code is disclosed. The method includes determining a size of the parity check matrix based on a coding rate and a codeword length; dividing a parity check matrix with the determined size into a predetermined number of blocks; classifying the blocks into blocks corresponding to the information part; arranging permutation matrixes in predetermined blocks from among the blocks classified as the first parity part, and arranging identity matrixes in a full lower triangular form in predetermined blocks from among the blocks classified as the second parity part; and arranging the permutation matrixes in the blocks classified as the information part such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code.

La présente invention concerne procédé de génération de matrices de vérification de parité d'un bloc de code LDPC. Ce procédé consiste à déterminer une taille de matrice de vérification de parité à partir d'un débit de codage et d'une longueur de mot de code, à diviser une matrice de vérification de parité de la taille déterminée en un certain nombre de blocs prédéterminés, à classer ces blocs en blocs correspondant à la partie information, à agencer des matrices de permutation en blocs prédéterminés provenant de blocs classés dans la première partie de parité, à agencer des matrices d'identité strictement triangulaire inférieure en blocs prédéterminés provenant des blocs classés dans la seconde de partie de parité et, à agencer les matrices de permutation dans les blocs classés dans la partie information de sorte qu'une longueur de cycle minimum soit maximisée et que des valeurs de pondération soient irrégulières sur un graphe de facteurs du bloc de code LDPC.

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