G - Physics – 06 – F
Patent
G - Physics
06
F
354/222
G06F 11/00 (2006.01) G06F 9/32 (2006.01) G06F 11/07 (2006.01) G06F 11/36 (2006.01)
Patent
CA 1303745
ABSTRACT In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic 'O' signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic 'O' signal is found therein, an exception signal is generated and applied to the control program of the data processing system.
570920
Bhandarkar Dileep
Cardoza Wayne
Cutler David N.
Orbits David A.
Witek Richard T.
Digital Equipment Corporation
Smart & Biggar
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