Apparatus and method for expediting subtraction procedures...

Details Apparatus and method for expediting subtraction procedures... Apparatus and method for expediting subtraction procedures...

G - Physics

06

F

354/167

G06F 7/52 (2006.01)

Patent

CA 1288868

ABSTRACT In a multiplier unit implemented with carry/save adder stages and executing a modified Booth algorithm, the signals, required to complete the 2's complement in order to perform a subtraction operation during the multiplication procedure using carry/save adder cells, are entered in the first carry/save stage in the appropriate carry/save cell positions. In this manner, one less signal is processed by the time-critical least significant cell associated with each carry/save adder stage, thereby reducing the overall time delay associated with the multiplier unit and accelerating the multiplication operation.

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