G - Physics – 06 – F
Patent
G - Physics
06
F
354/204
G06F 7/50 (2006.01) G06F 5/01 (2006.01)
Patent
CA 1311848
ABSTRACT The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs. Moreover, the pre-round logic supplies a carry bit to the full-precision adder/subtractor thus saving the time associated with a full-precision rounding bit addition. Thus, this low-precision floating-point addition/subtraction technique results in a significant enhancement of performance in floating-point addition/subtraction.
595322
Harrington Kathleen P.
Zurawski John H.
Digital Equipment Corporation
Smart & Biggar
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