G - Physics – 06 – F
Patent
G - Physics
06
F
354/138, 354/175
G06F 17/14 (2006.01)
Patent
CA 1308488
B1112662 ABSTRACT OF THE DISCLOSURE A digital array signal processor and associated method are described for implememting the fast Fourier transform radix-4 butterfly algorithm. The digital array signal processor is an integrated circuit with a four stage pipeline and can perform a radix-4 butterfly operation on four complex operands every 80 nanoseconds. Using the decimation-in-frequency implementation of the radix-4 butterfly algorithm, the digital array signal processor includes a first stage for distribution of complex input operand values, a second stage for performing addition and subtraction operations, a third stage for performing multiplication operations and a fourth stage for distribution of the output operand values. The digital array signal processor can be reconfigured to perform a radix-2 butterfly operation on two sets of two complex numbers during the 80 nanosecond machine cycle. The digital signal array processor can be configured to perform a series of operations on an array of operands or can be one of a series of processors, each processor performing a separate operation on an operand array.
590954
Fleming Michael E.
Furman Christopher D.
Magar Surendar S.
Murphy Kenneth N.
Rishavy Kevin M.
Array Microsystems Inc.
Fleming Michael E.
Furman Christopher D.
Gowling Lafleur Henderson Llp
Magar Surendar S.
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