Apparatus and method for providing a cache memory unit with...

Details Apparatus and method for providing a cache memory unit with... Apparatus and method for providing a cache memory unit with...

G - Physics

06

F

354/244

G06F 12/08 (2006.01)

Patent

CA 1277044

DEC662 ABSTRACT A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle the data signal group is stored in a temporary storage unit while a determination is made if the address associated with the data signal group is present in the cache memory unit. When the address is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage can occur during any free cycle.

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