G - Physics – 06 – F
Patent
G - Physics
06
F
354/223
G06F 11/08 (2006.01) G06F 11/10 (2006.01) H03M 13/00 (2006.01) H03M 13/19 (2006.01)
Patent
CA 1093213
ABSTRACT OF THE DISCLOSURE Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plural- ity of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them gener- ate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are opera- tive to generate a number of syndrome bits having a predeter- mined characteristic for indicating the existence of an un- correctable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.
285459
Barlow George J.
Nibby Chester M. Jr.
Honeywell Information Systems Inc.
Smart & Biggar
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