Apparatus and method for validating a computer model

Details Apparatus and method for validating a computer model Apparatus and method for validating a computer model

G - Physics

06

N

G06N 5/00 (2006.01) G06F 9/445 (2006.01)

Patent

CA 2446865

An apparatus and method for validating (602) a computer model (100) is described (204). In one embodiment, a computer readable medium (115) comprises instructions to associate a set of configurations of a computer model with a stimulus-response test, each configuration of the set of configurations representing a different model scenario, the stimulus-response test defining a modification to each configuration of the set of configurations (702). The computer readable medium (115) also comprises instructions to apply the stimulus-response test to the set of configurations to produce a simulated response for each configuration of the set of configurations and instructions to compare the simulated responses for the set of configurations with an expected response to the stimulus-response test.

L'invention concerne un appareil et un procédé conçus pour valider un modèle informatique. Dans un mode de réalisation de la présente invention, un support lisible par un ordinateur comprend des instructions permettant d'associer un ensemble de configurations d'un modèle informatique à un test de stimulus-réponse, chaque configuration de l'ensemble de configurations représentant un scénario de modèle différent, et le test de stimulus-réponse définissant une modification affectant chacune desdites configurations. Ce support lisible par un ordinateur comporte également des instructions permettant d'appliquer le test de stimulus-réponse audit ensemble de configurations afin de produire une réponse simulée pour chacune desdites configurations. Ledit support comprend en outre des instructions permettant de comparer les réponses simulées pour l'ensemble de configurations à une réponse attendue au test de stimulus-réponse.

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