Apparatus for accelerating store operations in a risc computer

G - Physics – 06 – F

Patent

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Details

354/230.87

G06F 9/312 (2006.01) G06F 9/30 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2026225

A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an instruction including addresses of registers to be read and written to, a multiplexor, and apparatus for controlling the multiplexor to transfer the address from a write position of the instructionregister to one of the read ports on the clock cycle following a store instruction.

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