Apparatus for and method of synchronizing a clock signal

H - Electricity – 04 – L

Patent

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Details

H04L 7/027 (2006.01) H04B 1/40 (2006.01) H04L 7/033 (2006.01) H04Q 7/22 (2006.01) H04Q 7/32 (2006.01)

Patent

CA 2102406

The present disclosure includes a discussion of a method of synchronizing a sampling clock signal to a received data signal (131). The clock recovery circuit (127) generates several clock signals (339 341, 343, 345) at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry (127) generates error signals (347 349, 351 353) representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals (347, 349, 351, 353) are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit (127) then adjusts or maintains the phase of the symbol clock (139) to provide the optimal sampling phase.

La présente invention est une méthode de synchronisation de signaux d'horloge échantillons et de signaux de données reçus (131). Le circuit de recouvrement de signaux d'horloge (127) produit plusieurs signaux d'horloge (339, 341, 343, 345) au débit des symboles, chaque signal d'horloge ayant sa phase particulière. Pour permettre de réaliser une acquisition initiale rapide, l'ensemble de signaux d'horloge contient une paire de signaux d'horloge dont les phases diffèrent l'une de l'autre d'un intervalle de symbole. Par ailleurs, le circuit de recouvrement de signaux d'horloge (127) produit des signaux d'erreur (347, 349, 351, 353) qui représentent la différence entre la phase du signal de données reçu et celle de chaque signal d'horloge. Ces signaux d'erreur (347, 349, 351, 353) sont traités durant plusieurs périodes de symbole pour déterminer la phase d'échantillonnage optimale. Le circuit de recouvrement de signaux d'horloge (127) ajuste alors la phase du signal d'horloge de symbole (139) ou la maintient fixe pour optimiser la phase d'échantillonnage.

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