Apparatus for controlling the access of processors at a data...

G - Physics – 06 – F

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354/234

G06F 3/00 (2006.01) B66B 1/18 (2006.01) G06F 9/46 (2006.01) G06F 13/374 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1171971

379 CAN INVENTORS: PAUL FRIEDLI and HANS GERHARD SUSS INVENTION: APPARATUS FOR CONTROLLING THE ACCESS OF PROCESSORS AT A DATA LINE ABSTRACT OF THE DISCLOSURE An apparatus for controlling the access of a plurality of microprocessors at a data line. The micropro- cessors are connected by interface components or blocks, logic switching circuits and bus drivers with two lines or conductors. By means of an access requisition or demand of a processor there is initiated a signal change of the first line. This signal change causes the transformation of data which is specific to the processor into a delay of a priority signal, upon the occurrence of which there is accomplished a signal change of the second line. As a function thereof there appears at an input of the interface component a signal change which is indicative of the availability of the data line. Upon simultaneous occurrence of access requisitions or demands of a number of processors the signal change of the second line is brought about by that pro- cessor whose priority signal possesses the smallest delay. The signal change of the second line prevents the occurrence of the priority signals possessing the greater time-delays and which are correlated to the remaining processors. At these processors there thus cannot occur any signal change at the input of the related interface component or block and which indicates the availability of the data line.

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