Apparatus for minimizing the performance degradation due to...

Details Apparatus for minimizing the performance degradation due to... Apparatus for minimizing the performance degradation due to...

G - Physics

06

F

354/239

G06F 12/10 (2006.01) G06F 12/02 (2006.01) G11C 8/00 (2006.01)

Patent

CA 1191967

IMPROVED APPARATUS FOR MINIMIZING THE PERFORMANCE DEGRADATION DUE TO ADDRESS TRANSLATION IN COMPUTER SYSTEMS EMPLOYING RANDOM ACCESS MEMORY AND PAGING Abstract A means for maximizing systems performance in computer systems which translate virtual initial addresses into real addresses utilizing addressable memory and substitute paging by not translating virtual address bits that are also real address bits and by commencing memory access using the available real address bits as they are available.

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