Apparatus for symmetrically truncating two's complement...

Details Apparatus for symmetrically truncating two's complement... Apparatus for symmetrically truncating two's complement...

G - Physics

06

F

350/57, 354/67

G06F 7/38 (2006.01) G06F 7/48 (2006.01)

Patent

CA 1228156

ABSTRACT There is described an arrangement for truncating two's complement numbers in a symmetrical manner so that truncated values of both positive and negative numbers tend toward zero. Symmetrical truncation is performed by discarding the least significant bits (LSB's) of positive values and by algebraically adding "one" to the truncated negative value when at least one of the discarded LSB's is a logical "one" value. An illustrated arrangement to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.

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