Apparatus for variable word length computing in an array...

G - Physics – 06 – F

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G06F 15/80 (2006.01) G06F 7/575 (2006.01) G06F 9/302 (2006.01) G06F 13/16 (2006.01) G06F 15/173 (2006.01)

Patent

CA 2478571

A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.

Une unité de calcul comprend un processeur comportant une pluralité de processeurs élémentaires qui ont chacun une unité de logique arithmétique, et un dispositif de commande qui commande les processeurs élémentaires. Le processeur peut envoyer un bit respectif d'un mot à bits multiples à chacun des processeurs élémentaires et assure la transmission des signaux entre les unités de logique arithmétique pour permettre aux unités d'effectuer une opération parallèle sur les bits du mot à plusieurs bits. Un ensemble de circuits d'extension est prévu pour coupler sélectivement une ou plusieurs unités de calcul ensemble afin de combiner leur capacité de traitement parallèle.

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