Apparatus, including delay means, for sampling and...

Details Apparatus, including delay means, for sampling and... Apparatus, including delay means, for sampling and...

H - Electricity

03

K

340/205, 352/38

H03K 5/00 (2006.01) G11B 20/14 (2006.01)

Patent

CA 1073115

ABSTRACT Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.

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