Arbitration of packet switched busses, including busses for...

Details Arbitration of packet switched busses, including busses for... Arbitration of packet switched busses, including busses for...

G - Physics

06

F

G06F 13/366 (2006.01) G06F 13/364 (2006.01)

Patent

CA 2051029

An arbiter is provided for resolving contention on synchronous packet switched busses, including busses composed of a plurality of pipelined segments, to ensure that all devices serviced by such a bus are given fair, bounded time access to the bus and to permit such devices to fill all available bus cycles with packets. Flow control for shared memory multiprocessors is readily implemented with this arbiter because the arbiter supports different types of arbitration requests and the prioritization of such arbitration requests by type.

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