Arbitration technique for a split transaction bus in a...

Details Arbitration technique for a split transaction bus in a... Arbitration technique for a split transaction bus in a...

G - Physics

06

F

354/234

G06F 13/36 (2006.01) G06F 13/18 (2006.01)

Patent

CA 1310762

ARBITRATION TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM Abstract of the Disclosure An arbitration technique for a split transaction bus of a computer system obtains higher data throughput as a result of giving responders (e.g. memories) absolute pri- ority over initiators (e.g. processors and I/O adapters), as a result of assigning all responders a higher priority than any initiator. Precedence is also given to retrying initiators which failed to complete a transaction because the module to which the transfer was addressed was busy. the requests from non-retrying initiators are temporarily rescinded to give precedence to the requests from retrying initiators. There is an absolute limit or bound to the number of requests which a retrying module may make before it is granted mastership of the bus to accomplish its transfer. To accomplish test and set and memory scrub transactions with a minimum time loss, the bus of the computer system creates a null conductivity cycle immediately following the cycle in which the address of the memory location to be tested and set or scrubbed is transferred.

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