G - Physics – 01 – R
Patent
G - Physics
01
R
356/24, 354/75
G01R 31/28 (2006.01) G01R 31/3167 (2006.01) G06J 1/00 (2006.01)
Patent
CA 1290464
ABSTRACT OF THE DISCLOSURE An architecture and device for testing mixed analog and digital VLSI circuits, wherein the digital circuit portions of the chip are grouped into a digital block, and the analog circuit portions of the chip are grouped into an analog block. Analog signals are pro- vided to the digital block through an A/D transducer, and digital signals are provided to the analog block through a D/A transducer. The analog and digital blocks may be isolated from each other by a digital input mul- tiplexer disposed between the A/D transducer and the digital block, and by an analog input multiplexer dis- posed between the D/A transducer and the analog block. To minimize the number of pins required to implement the architecture, multiplexers are connected to accessed circuit nodes in the analog block and the digital block for selectively communicating signals from the accessed nodes to external output pins.
599524
Fasang Patrick P.
Mullins Daryl E.
Fasang Patrick P.
Mullins Daryl E.
National Semiconductor Corporation
Smart & Biggar
LandOfFree
Architecture and device for testable mixed analog and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Architecture and device for testable mixed analog and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture and device for testable mixed analog and... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1318501