Architecture and method for combining static cache memory...

Details Architecture and method for combining static cache memory... Architecture and method for combining static cache memory...

G - Physics

11

C

G11C 7/00 (2006.01) G06F 12/08 (2006.01) G06F 13/28 (2006.01)

Patent

CA 2079690

ABSTRACT An embodiment of the present invention is a 1,024 by 1,024 DRAM integrated with a 1,024 by one SRAM. The SRAM contents can be directly addressed by external memory accesses and will service data transfers much faster than the DRAM could. The SRAM carries 64 lines of 16-bits of DRAM data. When an external write or read addresses a line of DRAM not in the SRAM, the SRAM flushes a line to update a previously cached line of DRAM, and then downloads a line of DRAM that contains a currently requested data bit.

Affiliated with

Also associated with

Rating

Architecture and method for combining static cache memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture and method for combining static cache memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture and method for combining static cache memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1637264