Architecture and methods for a hardware description language...

Details Architecture and methods for a hardware description language... Architecture and methods for a hardware description language...

G - Physics

06

F

G06F 17/50 (2006.01)

Patent

CA 2185908

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

La présente invention concerne l'obtention de la synthèse d'un circuit numérique à partir de la description textuelle d'un système numérique. La phase de synthèse consiste à construire et mémoriser un arbre d'analyse comportant des noeuds d'analyse. Le procédé consiste ensuite à mémoriser les relations entre les noeuds d'analyse et les synthèses d'éléments du circuit obtenues à partir des noeuds d'analyse. En partant de ces relations, il est possible d'établir la corrélation entre les résultats d'analyse associés aux éléments de circuit et le texte ayant servi à la génération de ces éléments de circuit. En l'occurrence, les résultats d'analyse peuvent être repris pour définir les caractérisitques d'affichage telles que la police de caractères ou la grosseur du texte associé à ces résultats.

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