Architecture for small instruction caches

Details Architecture for small instruction caches Architecture for small instruction caches

G - Physics

06

F

354/239, 354/230

G06F 9/38 (2006.01)

Patent

CA 1228170

ABSTRACT ARCHITECTURE FOR SMALL INSTRUCTION CACHES A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18). whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction , i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table (16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.

482001

Affiliated with

Also associated with

Rating

Architecture for small instruction caches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture for small instruction caches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for small instruction caches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1209447