G - Physics – 06 – F
Patent
G - Physics
06
F
354/166
G06F 7/00 (2006.01) G06F 5/01 (2006.01)
Patent
CA 2038673
Abstract of the Disclosure An arithmetic shift circuit includes a register, a first selecting means, a logic shifter, and a second selecting means. The register receives and stores an operand including a sign portion, and a shift amount. The first selecting means selectively outputs the operand and an inverted value thereof in accordance with a value of the sign portion stored in the register. The logic shifter performs a logic shift-right operation of an output from the first selecting means in accordance with the shift amount stored in the register. The second selecting means selectively outputs an output from the shift means and an inverted value thereof in accordance with the value of the sign portion stored in the register.
Corporation Nec
Nakamura Toshihiko
Smart & Biggar
LandOfFree
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