Arrangement for a hardware matcher

G - Physics – 06 – F

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354/230, 354/230

G06F 9/46 (2006.01) G06F 11/34 (2006.01) G06F 11/36 (2006.01) G06F 11/25 (2006.01)

Patent

CA 1229418

AN ARRANGEMENT FOR A HARDWARE MATCHER ABSTRACT OF THE DISCLOSURE This invention discloses a circuit for examining the value transmitted via a digital bus. A determination is made as to whether the value matches a predefined programmable value. An output indication is given for a match. In addition, this circuit may examine the transmitted value to determine whether it is within the bounds of a predefined range of values. This circuit utilizes a minimum of space and hardware components, due to its fabrication using RAM devices and a program logic array.

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