Arrangement for apportioning priority among co- operating...

Details Arrangement for apportioning priority among co- operating... Arrangement for apportioning priority among co- operating...

G - Physics

06

F

354/234

G06F 9/46 (2006.01) G06F 13/36 (2006.01) G06F 13/364 (2006.01) G06F 13/366 (2006.01) G06F 15/16 (2006.01)

Patent

CA 1241767

ABSTRACT OF THE DISCLOSURE A priority apportioning arrangement for computers that contain processors of two types connected to a common bus, namely a high-priority type which can determine its priority itself in relation to processors of a second low-priority type. The arrangement contains a first logic circuit which has its first input activated on a request for access from one of the low-priority units, its second input activated on a request for access from the high-priority unit, and its third activated during the whole time the bus is used, and has two outputs for assigning the bus a low- priority unit or the high-priority unit. A second logic circuit has two inputs, of which one senses that the high- priority unit desires access and the other senses that this access can take place with delay and two outputs, of which indicates to the first logic circuit that the access request from the high-priority unit is present, and the other indicates that the bus is occupied. When the input signal to the second logic circuit indicates that the assignment of the bus to the high-priority unit can take place with delay, the arrangement has time to assign the bus to a low-priority unit but the high-priority unit still has immediate access to the bus after termination of the task of the low-priority unit.

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