Arrangement for clock recovery

Details Arrangement for clock recovery Arrangement for clock recovery

H - Electricity

04

L

H04L 7/00 (2006.01) H04B 1/707 (2006.01)

Patent

CA 2083420

PHD 91.167 09.11.1992 ABSTRACT: Arrangement for clock recovery. The invention relates to an arrangement for clock recovery of a clock signal (t) from a data signal (d), comprising a data decision circuit (11) timed with the clock signal (t) to produce a decided data signal (c) on the basis of the data signal (d) and including a voltage-controlled oscillator (12) with a loop filter (13) preceding in the arrangement to produce the clock signal (t) on the basis of a control signal (k) that can be derived from the data signal (d) and the decided data signal (e). The arrangement is to be easily integrable. There is proposed that for producing the control signal (k) a DLL (Delay-Locked-Loop) correlation means (14) is provided. The arrangement may then be structured as a DLL delay correlator or as a DLL filter correlator. Drawing Figure 1.

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