Arrangement for clock supply of high bit rate switching...

Details Arrangement for clock supply of high bit rate switching... Arrangement for clock supply of high bit rate switching...

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/18 (2006.01) H03L 7/07 (2006.01) H03L 7/14 (2006.01)

Patent

CA 2317993

Arrangement for Clock Supply of High Bit Rate Switching Network Structures The invention is directed to on arrangement for clock supply of high bit-rate switching network structures in a digital narrow band switching system such as EWSD. A clock frequency signal (CLK2) traditionally generated with a crystal- controlled oscillator (11) as well as a corresponding frame clock signal (FMR2) are converted into low-voltage CMOS level signals and supplied to a system PL1 (2) for high frequencies. This contains a discretely constructed VCO 6 with a sine oscillator that derives a higher-frequency signal from the supplied clock signal and converts this into a high-frequency clocks signal (CLK92) of the output side. A feedback signal derived in this part serves as input-side feedback signal for a phase detector (8) in low-voltage CMOS technology. The feedback signal as well as the output-side high-frequency signal (CLK92) also serve for phase decoupling of the input-side frame clock signal (FMB2) from the output-side frame clock signal (FMB92) and for the phase-coupling thereof to the output-side high-frequency signal (CLK92). The input-side clock signals (CLK92, PMR92) arc distributed in pairs via a clock distribution system (3) dimensioned within narrow tolerances and are supplied to respective application-specific or, respectively, customized ~Cs (4) in low-voltage CMOS technology. This division onto various stages and onto components of different technologies in low-voltage technology allow the dimensioning and configuration with cost beneficial component.

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