Arrangement for generating a clock signal

Details Arrangement for generating a clock signal Arrangement for generating a clock signal

H - Electricity

04

L

328/87

H04L 7/02 (2006.01) H04L 7/033 (2006.01) H04L 25/49 (2006.01)

Patent

CA 1258101

Abstract "Arrangement for generating a clock signal." Arrangement for generating a clock signal from a biphase- modulated signal, comprising a controllable clock signal source. The polarity of the received signal (8) is sampled (9) at two sampling instants (LFR4, LFR7) having a fixed relationship. The polarity samples (B, F) are added modulo-2 (16) and the resultant signal (BF) controls the controllable clock signal source (VCO, 12). A false-synchronization detector comprises inter alia a modulo-2 adder (28) for comparing polarity samples in consecutive symbol intervals and a counter (27) for counting consecutively equal polarity samples (Fig. 4).

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