Arrangement for optimized utilization of i/o pins

Details Arrangement for optimized utilization of i/o pins Arrangement for optimized utilization of i/o pins

G - Physics

06

F

354/236

G06F 13/36 (2006.01) G06F 1/22 (2006.01) G06F 1/24 (2006.01) G06F 9/445 (2006.01)

Patent

CA 1216367

Abstract Arrangement For Optimized Utilization Of I/O Pins Arrangement for the input of address data to an integrated circuit (IC) via the same input/output (I/O) terminal pins utilized for the transfer of data is disclosed. The I/O data pins each have an output data latch and an address latch connected to the respective pin and positioned internally of the circuit's interface. A logic level is applied to each of those I/O data pins via a respective external resistor for normally biasing the pin to that logic level. A further I/O pin at the circuit's interface is connected to a common conductor positioned externally of the interface. Diodes are connected between selected ones of the I/O data pins and the common conductor in accordance with a desired address. A level controller responds to power-on-reset (POR) gating signal to switch the common conductor between a high impedance state and a logic level which effects conduction by the diodes, to enter address data bits. Address latches in the IC store the entered address data bits. The end of the gating signal enters the address bits into their respective latches. Output of data to the I/O data pins is via respective tri-stated transmit devices having their inputs connected to the outputs of respective data latches, and serves to extend that data value or its inverse to a respective I/O pin when enabled upon cessation of the POR signal.

463852

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