Arrangement for supervising a data processing system

Details Arrangement for supervising a data processing system Arrangement for supervising a data processing system

G - Physics

06

F

354/222

G06F 11/00 (2006.01) G06F 13/00 (2006.01)

Patent

CA 1223662

ABSTRACT OF THE DISCLOSURE A data processing system including an address bus connected to k computer elements is supervised with the aid of an arrangement comprising a plurality of indication registers connected to the bus and the an error signal genera- tor. The address bus is capable of transferring 2n>k binary addresses. The indication registers are each accessed by its address transferred through the bus, and each register stores an indication if its address is also assigned to one of the computer elements. The generator generates an error signal on reception of an indication that the instant address being transferred through the bus is not assigned a computer element.

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