Arrangement for switching over a clock pulse to a clock...

Details Arrangement for switching over a clock pulse to a clock... Arrangement for switching over a clock pulse to a clock...

H - Electricity

03

K

328/44

H03K 5/159 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2002733

88P177lE Abstract Arrangement for switching over a clock pulse to a clock pulse of the same frequency but with lagging clock phase With high switching speeds, switching operations in integrated switch-over arrangements cannot be suf- ficiently coordinated in terms of time. Spikes thereby resulting during switch-overs are to be avoided. The switch-over arrangement consists of a control logic circuit (1), a clock pulse monitor (2) and a clock pulse selector (3). The control logic circuit (1) con- tains a shift register with register cells (Z1 to Zn) which are all the same, apart from the first one. Those which are the same have a D-type flip-flop (H2 to Hn), in which a pre-control signal (St2* to Stn*) is formed by buffering a control signal (St1 to Stn-1). A pre-control signal (St1*) is produced in the first register cell (Z1) when all others (St2* to Stn*) are missing. Switching over is dependent on a correction signal (K) and the clock pulses at the relevant register cells, in such a way that the previous control signal is first switched off before the new control signal is switched on. In the clock pulse selector (3), the active control signal switches through the associated clock pulse as data auxiliary clock pulse (DHT). The clock pulse monitor (2) generates a start signal (Sta) if erroneously no control signals or several at the same time (from St1 to Stn) have been formed. The arrangement can be employed for timing recovery in digital signal multiplexing devices. Figs. 5a and 5b

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