Arrangement for synchronizing the phase of a local clock...

Details Arrangement for synchronizing the phase of a local clock... Arrangement for synchronizing the phase of a local clock...

H - Electricity

03

L

328/87

H03L 7/00 (2006.01) H03K 5/14 (2006.01) H03L 7/081 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1155932

11 PHN. 9677 ABSTRACT: Synchronizing the phase of a locally generated clock signal with the phase of an input signal is usually effected by using a phase-locked loop, but this has a drawback that a certain run-in time is necessary to be sure that the phase of the clock signal is stable. The present arrangement comprises a delay line having taps, the delay line being driven by a crystal oscillator. Clock signal versions Cl(0), Cl(90), Cl(180) and Cl(270) which are phase shifted relative to one another through 90° are available at the successive taps. A coincidence detection circuit comprising trigger circuits and a combining net- work detects the version of the clock signal whose ascend- ing edge, for example, is located nearest to an ascending edge of the data signal, and this version is supplied as the clock signal at an output by the selective control of switches by control signals from the outputs of the network.

369102

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