G - Physics – 06 – F
Patent
G - Physics
06
F
354/239
G06F 9/00 (2006.01) G06F 9/26 (2006.01) G06F 12/00 (2006.01) G06F 13/00 (2006.01) G11C 7/00 (2006.01) G11C 8/00 (2006.01) G11C 15/00 (2006.01) G11C 17/00 (2006.01) G11C 19/00 (2006.01) G11C 21/00 (2006.01) G11C 27/00 (2006.01) H04Q 3/545 (2006.01)
Patent
CA 1105149
Abstract of Disclosure: A sequence of control instructions and a number of insertion instructions are stored in memory element groups accessed by associated addresses. The sequence is read and decoded by means of successive address increase. In order to insert one of the insertion instructions between the control instructions, the sequence comprises an insertion reference indicating a first address assigned to the insertion instruction and a second address assigned to one of the control instructions. Upon decoding the insertion reference, a logical buffering unit is used in order to replace the successive address increase by such address transfers that the control instruction accessed by said second address is decoded subsequent to the insertion instruction which itself is decoded after the insertion reference.
296996
Marks & Clerk
Telefonaktiebolaget Lm Ericsson
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