Arrangement in the instruction unit of a microprogram-...

Details Arrangement in the instruction unit of a microprogram-... Arrangement in the instruction unit of a microprogram-...

G - Physics

06

F

354/230.72

G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/30 (2006.01) G06F 9/318 (2006.01)

Patent

CA 1191615

ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM-CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE-CONTROLLED EXECUTION OF PARTICULAR INSTRUCTIONS Abstract In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch is provided signalizing the instruction decoder whether micro program instructions or directly controlled macro instructions are to be executed. The microprogram instructions are executed in the usual manner. For the execution of the directly controlled macro instructions, the control storage of the processor is not required for supplying micro instructions. Instead, this storage with the operation decoder as an address supplies one or several hardware control words. The hardware control words consist of individual control bits, each of which directly controls one hardware function.

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