Array multiplier

Details Array multiplier Array multiplier

G - Physics

06

F

354/167

G06F 7/52 (2006.01) G06F 7/50 (2006.01)

Patent

CA 2038422

C0644/7001 ABSTRACT ARRAY MULTIPLIER A CMOS array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single FET switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.

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