Assembly and method for testing integrated circuit devices

Details Assembly and method for testing integrated circuit devices Assembly and method for testing integrated circuit devices

G - Physics

01

R

G01R 1/06 (2006.01) G01R 31/3163 (2006.01) G01R 31/3181 (2006.01) G01R 31/319 (2006.01) G11C 29/24 (2006.01)

Patent

CA 2245549

A testing assembly (10), and an associated method, for testing an integrated circuit device (12). The testing assembly (10) is capable of testing an integrated circuit device (12) having a large number of input and output terminals formed of either single-ended terminals (16) or differential terminals (20, 22). Static testing, both functional and parametric, can be performed upon the integrated circuit device (12). Additionally, dynamic testing of the integrated circuit device (12), even integrated circuit devices operable at high frequencies, is possible through operation of the testing assembly (10). Test signals are applied by way of signal rails (54, 56, 58) to the device (12) undergoing testing. A test signal response indicator (78) is coupled to observe responses to the test signals.

Installation (10) et procédé de tests d'un circuit intégrés (12). L'installation (10) permet de tester un circuit intégré (12) comportant un grand nombre de bornes d'entrée et de bornes de sortie constituées soit par des bornes à extrémité unique (16) soit par des bornes différentielles (20, 22). Des tests statiques, portant à la fois sur les fonctions et les paramètres, peuvent être réalisés sur le circuit intégré (12). L'installation (10) permet en outre de tester dynamiquement le circuit intégré (12), même pour un circuit intégré fonctionnant à des fréquences élevées. Les signaux de test sont appliqués au circuit (12) soumis au test par des voies d'acheminement des signaux (54, 56, 58). Un indicateur de réaction aux signaux de tests (78) permet d'observer les réactions à ces signaux.

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