G - Physics – 06 – F
Patent
G - Physics
06
F
354/167, 354/230
G06F 9/38 (2006.01) G06F 7/52 (2006.01)
Patent
CA 1194606
ABSTRACT An associative processor is described wherein an array of associative processing cells is configured to achieve variable length fast multiplication of numbers, such as binary two's complement numbers, under mask control. A configuration suitable for signed multiplication is described wherein the processing sequences in all cells are compatable, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure is described, including an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.
433652
International Standard Electric Corporation
Smart & Biggar
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