Asynchronous fifo device comprising a stack of registers

Details Asynchronous fifo device comprising a stack of registers Asynchronous fifo device comprising a stack of registers

G - Physics

06

F

354/237, 354/241

G06F 13/00 (2006.01) G06F 5/08 (2006.01) G11C 19/00 (2006.01) H03K 23/66 (2006.01)

Patent

CA 1216371

ABSTRACT Asvnchronous FIFO device comprising a stack of registers An asynchronous FIFO device suitable for use as a buffer comprises a stack having a plurality of sec- tions. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX having a first input connected to receive a logic signal indicative of the condition of the prece- ding subassembly, a second input connected to receive a logic signal indicative of the condition of the follo- wing subassembly and an output connected to the associa- ted storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.

464349

Affiliated with

Also associated with

Rating

Asynchronous fifo device comprising a stack of registers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous fifo device comprising a stack of registers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous fifo device comprising a stack of registers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1236809