Asynchronous signal extracting circuit

Details Asynchronous signal extracting circuit Asynchronous signal extracting circuit

H - Electricity

04

J

H04J 3/00 (2006.01) H04J 3/06 (2006.01) H04J 3/07 (2006.01) H04L 5/24 (2006.01) H04L 7/08 (2006.01) H04L 25/05 (2006.01)

Patent

CA 2065853

An asynchronous signal extracting circuit for extracting asynchronous signals multiplexed in a synchronization frame, comprising a demultiplexer unit (1) that demultiplexes asynchronous signals and clock signals which are in synchronism with valid data in the asynchronous signals, a buffer memory (2) that writes valid data in the demultiplexed asynchronous signals using the clock signals as write clock signals, a phase-locked loop circuit (3) that forms read clock signals for the memory (2), and a control unit (51 that switches the frequency band of a low-pass filter (4) in the circuit (3) periodically or in response to a detection signal of pointer adjustment. The circuit suppresses low-frequency jitter contained in the read clock signals.

Circuit permettant d'extraire des signaux asynchrones multiplexés dans une trame de synchronisation. Comprend une unité de démultiplexage (1) pour démultiplexer des signaux asynchrones et des signaux d'horloge synchronisés avec des données valides des signaux asynchrones, une mémoire tampon (2) qui ajoute des données valides aux signaux asynchrones démultiplexés en utilisant les signaux d'horloge comme signaux d'horloge d'écriture, un circuit de verrouillage de phase (3) qui forme des signaux d'horloge de lecture pour la mémoire (2), et une unité de commande (5) qui commute la bande de fréquences d'un filtre passe-bas (4) du circuit (3) périodiquement ou en réponse à un signal de détection de réglage de pointeur. Le circuit supprime la gigue à basse fréquence des signaux d'horloge de lecture.

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