Asynchronous/synchronous data receiver circuit

Details Asynchronous/synchronous data receiver circuit Asynchronous/synchronous data receiver circuit

H - Electricity

04

L

340/205

H04L 7/02 (2006.01) H04L 7/10 (2006.01) H04L 7/033 (2006.01) H04L 7/04 (2006.01)

Patent

CA 1263464

-33- ABSTRACT In a communications system wherein a transmitted message is preceded only by an address, an asynchronous circuit (100) detects the address and provides an initializing signal (at Q-NOT of 105) to a synchronous clock recovery circuit (114 and 116) so that the first bit of the recovered clock signal (at Q3 of 114) is synchronized to the first bit of the message. During the transmission of the message the synchronous clock recovery circuit makes minor adjustments to the phase of the recovered clock to maintain synchronization between the recovered clock and the message. At the termination of the message, the synchronous clock recovery circuit is inhibited (by Q of 106) until the asynchronous circuit detects another address.

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