Asynchronous time division multiplex switching system

Details Asynchronous time division multiplex switching system Asynchronous time division multiplex switching system

H - Electricity

04

Q

H04Q 11/04 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2042031

(57) Abstract This invention relates to an ATDM switching comprising a serial to parallel converter (100) arranged to receive in- coming packets of data (which include their own routing information) from several input ports (107) in serial formal and deliver them, in parallel format, to a Random Access Memory (RAM) (101, 102) in such a way that the packets form queues within the memory, one for each output port. Packets are then transferred in parallel format, one from each queue in turn, to a parallel to serial converter (105) which delivers them to their respective output ports (109) in serial format. The arrangement is such that when the memory becomes full the system can accommodate incoming packets by overwriting data in the longest queue, a tech- nique that can significantly reduce the total number of packets lost during long term operation.

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