Asynchronously equilibrated and pre-charged static ram

Details Asynchronously equilibrated and pre-charged static ram Asynchronously equilibrated and pre-charged static ram

G - Physics

11

C

352/40

G11C 15/04 (2006.01) G11C 7/00 (2006.01) G11C 11/419 (2006.01)

Patent

CA 1177170

ASYNCHRONOUSLY EQUILIBRATED AND PRE-CHARGED STATIC RAM ABSTRACT OF THE DISCLOSURE A static RAM (random access memory) is described wherein fully asynchronous active equilibration and pre- charging of the RAM's bit lines provides improved memory access time and lower active power dissipation. In the preferred embodiment, each change in the memory's row address is sensed for developing a clock pulse of a controlled duration. The clock pulse is received by a group of equilibrating transistors and a group of pre- charging transistors which are coupled to the memory's bit lines. When the clock pulse occurs, all the above- mentioned transistors conduct to effect simultaneous equilibration and pre-charging of the bit lines.

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