Atm queuing and scheduling apparatus

Details Atm queuing and scheduling apparatus Atm queuing and scheduling apparatus

H - Electricity

04

L

H04L 12/56 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2144147

The apparatus comprises a buffer store connected to an input line upon which ATM cells are received, and an output line upon which ATM cells are transmitted. A control means receives, for each cell, a channel identifier and a path identifier from which a first signal is generated indicative of a maximum delay value which is applied to the buffer store and used to schedule the particular cell for transmission, on a calendar controlling a sustainable cell rate. The control means generates a second signal indicative of a minimum delay value which is applied to the buffer means and, in conjunction with said first signal is used to schedule the particular cell for transmission, on a calendar controlling the peak cell rate. The apparatus can also handle routing information, where a group of channel connections define a Route which share a peak cell rate for the Route and are scheduled on the peak cell rate calendar.

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