Auto-zero sample and hold circuit

Details Auto-zero sample and hold circuit Auto-zero sample and hold circuit

G - Physics

11

C

328/171

G11C 27/02 (2006.01)

Patent

CA 1230168

11 ABSTRACT A sample and hold circuit contains a pair of dif- ferential amplifiers (A1 and A2) switchably arranged in series. The circuit input signal (VIN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) pro- vides the circuit output signal (VOLT) during hold. Switch- ing circuitry (S1, S2 and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

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