Automatic clock phase adjustment method and circuit

Details Automatic clock phase adjustment method and circuit Automatic clock phase adjustment method and circuit

G - Physics

06

F

340/165, 354/231

G06F 1/04 (2006.01) H03K 5/13 (2006.01) H04L 7/033 (2006.01) H04L 25/05 (2006.01)

Patent

CA 1106502

ABSTRACT OF THE DISCLOSURE An automatic clock phase adjustment circuit is incorporated in a local unit of a data clocking system. The local unit also includes a clock pulse generator and a local data storage device. The system also includes a remote unit having a remote data storage device. The automatic clock phase adjustment circuit receives clock pulses from the generator and produces output clock pulses having first and second half periods interconnected by a clocking transition which when applied to the remote storage device causes clocking out of data to the local storage device. The circuit also produces a sampling pulse during each of the first and second half periods of the output clock pulses and is operable to detect in which particular one of the half periods a positive transition in the incoming data has occurred during the interval of a sampling pulse in that half period. This permits the circuit to produce local or input clock pulses for clocking in the incoming data at the local storage device during the other of the half periods so that the clocking edges of the input clock pulses will not coincide with any of the positive transitions of the incoming data when applied to the local storage device. As a result, reliable storage of the incoming data is guaranteed to occur at the local storage device at times when the data is stable. -1-

312610

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