Automatic layout for cascode voltage switch logic

Details Automatic layout for cascode voltage switch logic Automatic layout for cascode voltage switch logic

G - Physics

06

F

328/127, 354/46

G06F 17/50 (2006.01)

Patent

CA 1241115

ABSTRACT AUTOMATIC LAYOUT FOR CASCODE VOLTAGE SWITCH LOGIC A method for automatically laying out a circuit starting from a logic gate diagram, especially for a CMOS technology. The logic is divided into blocks having a maximum number of serially connected transistors. Then the transistors are ordered to maximize the number of contiguously connected transistors. The ordered transistors then have their remaining connections determined according to the type of logic gate they represent.

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