Autonomously cycling data processing architecture

Details Autonomously cycling data processing architecture Autonomously cycling data processing architecture

G - Physics

06

F

G06F 3/13 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2304609

An electronic data processing circuit (4) is disclosed having at least an instruction memory (202), an instruction decoder (205), and a slot structure (209). The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register, (2) a data register, (3) a function register, and (4) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.

On décrit un circuit (4) électronique de traitement de données comprenant au moins une mémoire (202) d'instructions, un décodeur (205) d'instructions et une structure (209) à fentes. La structure à fentes se caractérise par une pluralité de fentes. Chaque fente comporte au moins: (1) un registre d'adresses, (2) un registre de données, un registre de fonctions et (4) un circuit de surveillance. Chaque fente exécute de manière asynchrone des opérations définies par le contenu informatif de son registre d'adresses respectif, de son registre de données respectif et de son registre de fonctions respectif lorsque la totalité de l'information est présente.

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