Avoiding latent errors in a logic network for majority...

Details Avoiding latent errors in a logic network for majority... Avoiding latent errors in a logic network for majority...

G - Physics

06

F

354/222

G06F 11/18 (2006.01) H03K 19/173 (2006.01) H03K 19/23 (2006.01)

Patent

CA 2032519

A circuit and a method for avoiding latent errors in a logic network for majority selection of binary signals in a triplicated system. Errors which result from errors or faults in one of two or more parallel-connected transistors of one or more separate logic devices included in the logic network are avoided by repeatedly switching each of the separate logic devices in a manner such that transistors which were parallel-connected become series-connected, and vice versa. As a result, these devices will perform alternately logic operations which are the dual correspondence of one another, e.g. NAND- and NOR-operations with the aid of the same transistors in both instances. Thus, in practice, majority selection will be performed alternately with two mutually different logic networks, which are the dual correspondence of each other.

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