Back illuminated imager with enhanced uv to near ir sensitivity

Details Back illuminated imager with enhanced uv to near ir sensitivity Back illuminated imager with enhanced uv to near ir sensitivity

H - Electricity

01

L

H01L 31/18 (2006.01) H01L 21/00 (2006.01) H01L 21/30 (2006.01) H01L 21/301 (2006.01) H01L 21/46 (2006.01) H01L 21/78 (2006.01) H01L 27/00 (2006.01) H01L 27/12 (2006.01) H01L 27/146 (2006.01) H01L 27/148 (2006.01) H01L 31/10 (2006.01)

Patent

CA 2434252

The present invention is a back illuminated image array device (10) and a method of constructing such a device. The device (10) is generally comprised of an array circuitry layer (16), a front layer (14), and a quartz layer (12). The array circuitry layer (16) is defined on one surface of the front layer (14). The quartz layer (12) is mounted on the other surface of the front layer (14). The method of fabricating the device is generally comprised of the following steps The method provides a wafer (30) having a thick silicon layer (32), an oxide layer (34) on the thick silicon layer (32), and a front silicon layer (36) on the oxide layer (34). The front layer (36) has a first surface and a second surface with the second surface proximal to the oxide layer. Array circuitry is formed on the first surface of the front layer. A temporary layer (40) is applied to the surface of the array circuitry (24). The thick silicon layer (32) and the oxide layers (34) are removed from the wafer (30), thereby, exposing the second surface of the front layer. A quartz layer is applied to the second surface. The temporary layer (40) is removed from the array surface.

L'invention porte sur un afficheur (10) à matrice éclairé par l'arrière et sur son procédé de construction. Ledit afficheur (10) comporte d'une manière générale une couche matrice de circuits (16), une couche frontale (14), et une couche de quartz (12), la couche matrice de circuits (16) étant disposée sur l'une des faces de la couche frontale (14) et la couche de quartz, sur l'autre face de la couche frontale (14). Le procédé de fabrication du dispositif comporte d'une manière générale les étapes suivantes: partir d'une tranche (30) de silicium présentant une couche épaisse (32) de silicium, une couche d'oxyde (34) disposée sur la précédente (32), et une couche frontale (36) de silicium disposée sur la précédente (34), la couche frontale (36) présentant une première surface, et une deuxième surface proche de la couche d'oxyde; former la matrice de circuits sur la première surface de la couche frontale; appliquer une couche provisoire (40) sur la surface de la matrice de circuits (24); éliminer de la tranche la couche épaisse (32) de silicium et les couches d'oxyde (34) pour exposer la deuxième surface de la couche frontale; appliquer une couche de quartz sur la deuxième surface; éliminer la couche provisoire (40) de la surface de la matrice.

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